This invention is in the field of semiconductor integrated circuits. Embodiments of this invention are directed to uniformity of recess etch processes in connection with forming embedded silicon alloy structures.
Recent advances in semiconductor technology as applied to integrated circuits include the use of “strain engineering” (or, alternatively, “stress engineering”) in the manufacture of semiconductor device structures. It has been discovered that the tuning of strain in the crystal lattice of metal-oxide-semiconductor (MOS) transistor channel regions can enhance carrier mobility in those regions. As is fundamental in MOS device technology, the source/drain current (i.e., drive) of an MOS transistor in both the triode and saturation regions is proportional to carrier mobility in the channel region. In a general sense, compressive stress enhances hole mobility in the channel region of a p-channel MOS transistor, and tensile stress enhances electron mobility in the channel region of an n-channel MOS transistor. Typically, p-channel MOS transistors exhibit lower drive capability than n-channel MOS transistors in typical modern integrated circuits. As such, strain engineering techniques are more typically applied to p-channel MOS transistors than to n-channel MOS transistors, in current day manufacturing technology.
Various strain engineering approaches are known in the art. According to the approach known as “embedded SiGe” (also referred to as “eSiGe”), the source and drain regions of a p-channel MOS transistor structure are etched from the silicon substrate or well region, and are replaced with a silicon-germanium alloy formed by selective epitaxy. Because of the germanium atoms within the crystal lattice, the germanium constituting as much as 25% to 30% (atomic) of the alloy, eSiGe exhibits a larger lattice constant than does silicon (i.e., the distance between unit cells in the crystal lattice for SiGe is greater than in single-crystal silicon). Embedded eSiGe source/drain regions thus apply compressive stress to the channel region of the p-channel MOS transistor being formed. This compressive stress in the channel increases the hole mobility of the p-channel MOS transistor, and enhances its performance.
A similar approach for improving carrier mobility is known for n-channel MOS transistors. Commonly assigned U.S. Pat. No. 7,023,018, incorporated herein by reference, describes the use of silicon-carbon alloy material as source/drain structures in n-channel MOS transistors. As described in that U.S. Patent, silicon-carbon source/drain structures cause an increase in tensile stress in a direction parallel to the intended direction of source/drain current flow in the transistor. This tensile stress in the source/drain regions increases tensile strain in the p-type channel region between the source and drain structures, which increases electron mobility in that channel region and thus improves the performance of the n-channel MOS transistor.
FIGS. 1a through 1d illustrate, in cross section, the fabrication of a conventional p-channel MOS transistor including eSiGe source/drain regions. FIG. 1a illustrates a portion of the integrated circuit structure including p-type substrate 4, with n-well 6 formed at selected locations of the surface of substrate 4, by way of ion implantation and diffusion in the conventional manner. Shallow trench isolation structures 5 are disposed at selected locations of the surface of substrate 4, formed by conventional etch and deposition processes. At the stage of the process shown in FIG. 1b, thermal oxidation or deposition of gate dielectric 7 has been followed by the deposition, photolithography, and etch of polysilicon gate structure 8. In this example, hard mask 9 is used to protect polysilicon gate structure 8 from the polysilicon etch, and remains in place. Typically, a “re-oxidation” of the patterned polysilicon is performed after its etch, resulting in thin oxide layer 11 on the side surfaces of polysilicon gate structure 8. Sidewall dielectric spacers 13 are formed on the sidewalls of gate structure 8 at this point by deposition and anisotropic etch, and will define more lightly-doped source/drain extensions as known in the art.
To form the embedded SiGe source/drain regions in this conventional process, remaining gate dielectric 7 is removed from the source/drain regions, and exposed locations of n-well 6 are etched, at locations outside of gate electrode 8 and sidewall spacers 13, to form recesses 10 into the underlying single-crystal silicon as shown in FIG. 1c. Hard mask 9 protects gate structure 8 from this recess etch. Recesses 10 are thus located at the source/drain regions of the transistor being formed at this location of substrate 4, and are essentially self-aligned with gate structure 8 but with some lateral etch occurring under sidewall spacers 13 as will be discussed in further detail below.
In conventional processes, the recess etch begins with an initial timed dry “breakthrough” etch that etches the implanted region at the surface (e.g., the result of a blanket implant setting the transistor threshold voltage). After this initial etch, a plasma etch under isotropic conditions is then performed, with the active species being either a fluorine-based (SF6 or NF3) or chlorine (Cl2), along with a diluent such as helium, argon, or another inert gas, or in some cases oxygen. This isotropic plasma etch tends to etch the single crystal silicon at the same rate in all directions. To provide process control, the plasma etch is conventionally carried out under etchant-starved concentrations, with the etch rate controlled by the flow rate of the etchant species.
Alternatively, after the dry breakthrough etch and the dry isotropic etch, a subsequent wet etch can be employed to undercut gate structure 8 along the crystalline structure of the single crystal silicon. As known in the art, crystallographic wet silicon etch chemistry can provide a high degree of selectivity to the crystalline planes.
Following the recess etch of FIG. 1c, selective epitaxy of a silicon-germanium alloy is then performed, filling the recesses with embedded SiGe structures 12 as shown in FIG. 1d. Hard mask 9 remains in place over gate electrode 8, to prevent SiGe growth on the top surface of the polysilicon. SiGe structures 12 are typically doped in situ during the epitaxy, and also by subsequent ion implantation, to become heavily doped p-type, forming the source and drain regions of this transistor.
As suggested in FIG. 1d, embedded SiGe structures 12 exert compressive strain on channel region 17 underlying gate electrode 8, because the presence of germanium atoms increases the lattice constant of SiGe structures 12 relative to the surrounding silicon. This compressive strain increases the mobility of holes in channel region 17, enhancing the current drive of this p-channel transistor in an “on” state.
The strain that is exerted by embedded SiGe structures 12 upon channel region 17 depends, in large part, on the position of embedded SiGe structures 12 relative to the edge of gate electrode 8. The strain in channel region 17 increases as the embedded SiGe structures 12 more closely approach the gate edge (i.e., as the “SiGe to gate distance” shortens). And the greater the induced strain in channel region 17, the greater the improvement in carrier mobility in channel region 17. As such, conventional methods for performing the recess etch depicted in FIG. 1c intentionally include some amount of lateral etch under sidewall spacers 13. The extent and shape of lateral etch under sidewall spacers 13 thus define both the channel length of the transistor and the amount of induced strain in channel region 17.
It has been observed, however, that the extent of the lateral etch can be quite non-uniform within an integrated circuit, due to loading effects from neighboring geometries. More specifically, the SiGe-to-gate distance has been observed to vary as much as thirty percent, depending on the pitch (feature width plus spacing) of the source/drain regions being etched (or, indirectly, on the pitch of polysilicon gate electrodes 8 defining the location of the recess edges). This wide variation in lateral etch of the recesses causes widely varying transistor channel lengths and carrier mobility within those integrated circuits in which the gate electrode structures vary in width and spacing.
It has been observed, in connection with this invention, that the variation in undercut is not particularly well-behaved, in that it is difficult to correlate the undercut variation with the local density of source/drain recesses, the proximity of nearby recesses, the widths of specific features, and the like. As such, the ability to compensate for the effects of varying undercut at the design stage (i.e., by oversizing or undersizing the gate widths as patterned, at specific locations) is limited at best.
One could avoid the undesired effects of this undercut variation in several conventional ways. One approach would be to design the gate structures with a relatively constant width and spacing across the integrated circuit; however, this constraint would significantly reduce the ability of the designer to optimize the layout for device and circuit performance. Another approach would be to incorporate sacrificial “dummy” structures, such that the loading effects would be absorbed by non-functional structures. Of course, that approach consumes valuable chip area.
By way of further background, Yeom et al., “Polysilicon Etchback Plasma Process Using HBr, Cl2, and SF6 Gas Mixtures for Deep-Trench Isolation”, J. Electrochemical Soc., Vol. 139, No. 2 (1992), pp. 575-79, report increased lateral etching by high HBr gas mixture plasma etches, as applied to polysilicon etchback of polysilicon-filled deep trench isolation structures. The Yeom et al. paper also indicates that HBr and Cl2 gases are known to have low loading effects in plasma etches relative to fluorinated gases such as SF6 or CF4.